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MB85RS64A
? RDSR
The RDSR command reads status register data. After op-code of RDSR is input to SI, 8-cycle clock is input
to SCK. The SI value is invalid for this time. SO is output synchronously to a falling edge of SCK. Continuously
reading status register is enabled by keep on sending SCK before rising CS with the RDSR command.
C S
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
S CK
S I
0
0
0
0
0
1
0
1
Invalid
Data Out
S O
High-Z
M S B
L S B
Invalid
? WRSR
The WRSR command writes data to the nonvolatile memory bit of status register. After performing WRSR
op-code to a SI pin, 8 bits writing data is input. WEL (Write Enable Latch) is not able to be written with WRSR
command. a SI value correspondent to bit 1 is ignored. Bit 0 of the status register is fixed to “0” and cannot
be written. The SI value corresponding to bit 0 is ignored.
C S
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
S CK
Instruction
Data In
S I
0
0
0
0
0
0
0
1
7
6
5
4
3
2
1
0
M S B
L S B
S O
8
High-Z
DS501-00009-0v01-E
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